? semiconductor components industries, llc, 2005 december, 2005 ? rev. 3 1 publication order number: mcr8s/d mcr8sd, mcr8sm, MCR8SN preferred device sensitive gate silicon controlled rectifiers reverse blocking thyristors designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever half?wave, silicon gate?controlled devices are needed. features ? sensitive gate allows triggering by microcontrollers and other logic circuits ? blocking voltage to 800 volts ? on?state current rating of 8 amperes rms at 80 c ? high surge current capability ? 80 amperes ? rugged, economical to?220ab package ? glass passivated junctions for reliability and uniformity ? minimum and maximum values of igt, vgt and ih specified for ease of design ? immunity to dv/dt ? 5 v/ sec minimum at 110 c ? pb?free packages are available* maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive off?state voltage (note 1) (t j = ?40 to 110 c, sine wave, 50 to 60 hz, gate open) mcr8sd mcr8sm MCR8SN v drm, v rrm 400 600 800 v on-state rms current (180 conduction angles; t c = 80 c) i t(rms) 8.0 a peak non-repetitive surge current (1/2 cycle, sine wave, 60 hz, t j = 110 c) i tsm 80 a circuit fusing consideration (t = 8.33 ms) i 2 t 26.5 a 2 sec forward peak gate power (pulse width 1.0 s, t c = 80 c) p gm 5.0 w forward average gate power (t = 8.3 ms, t c = 80 c) p g(av) 0.5 w forward peak gate current (pulse width 1.0 s, t c = 80 c) i gm 2.0 a operating junction temperature range t j ?40 to 110 c storage temperature range t stg ?40 to 150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. v drm and v rrm for all types can be applied on a continuous basis. ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. scrs 8 amperes rms 400 thru 800 volts to?220ab case 221a?09 style 3 1 http://onsemi.com marking diagram a = assembly location y = year ww = work week x = d, m, or n g = pb?free package aka = diode polarity 2 3 device package shipping ordering information mcr8sd to?220ab 50 units / rail MCR8SN to?220ab 50 units / rail mcr8sdg to?220ab (pb?free) 50 units / rail MCR8SNg to?220ab (pb?free) 50 units / rail preferred devices are recommended choices for future use and best overall value. mcr8sm to?220ab 50 units / rail mcr8smg to?220ab (pb?free) 50 units / rail k g a pin assignment 1 2 3 anode gate cathode 4 anode ay ww mcr8sxg aka
mcr8sd, mcr8sm, MCR8SN http://onsemi.com 2 thermal characteristics characteristic symbol value unit thermal resistance, junction?to?case junction?to?ambient r jc r ja 2.2 62.5 c/w maximum lead temperature for soldering purposes 1/8 from case for 10 seconds t l 260 c electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics peak repetitive forward or reverse blocking current (note 3) (v d = rated v drm and v rrm ; r gk = 1 k )t j = 25 c t j = 110 c i drm , i rrm ? ? ? ? 10 500 a on characteristics peak forward on?state voltage (note 2) (i tm = 16 a) v tm ? ? 1.8 v gate trigger current (continuous dc) (note 4) (v d = 12 v; r l = 100 ) i gt 5.0 25 200 a holding current (note 4) (v d = 12 v, gate open, initiating current = 200 ma) i h ? 0.5 6.0 ma latch current (note 4) (v d = 12 v, i g = 200 a) i l ? 0.6 8.0 ma gate trigger voltage (continuous dc) (note 4) t j = 25 c (v d = 12 v; r l = 100 )t j = 40 c v gt 0.3 ? 0.65 ? 1.0 1.5 v gate non?trigger voltage t j = 110 c (v d = 12 v, r l = 100 ) v gd 0.2 ? ? v dynamic characteristics critical rate of rise of off?state voltage (v d = 67% v drm , r gk = 1 k , c gk = 0.1 f, t j = 110 c) dv/dt 5.0 15 ? v/ s critical rate of rise of on?state current ipk = 50 a, pw = 40 sec, dig/dt = 1 a/ sec, igt = 10 ma di/dt ? ? 100 a/ s 2. indicates pulse test: pulse width 2.0 ms, duty cycle 2%. 3. r gk = 1000 ohms included in measurement. 4. does not include r gk in measurement.
mcr8sd, mcr8sm, MCR8SN http://onsemi.com 3 + current + voltage v tm i drm at v drm i h symbol parameter v drm peak repetitive off state forward voltage i drm peak forward blocking current v rrm peak repetitive off state reverse voltage i rrm peak reverse blocking current v tm peak on state voltage i h holding current voltage current characteristic of scr anode + on state reverse blocking region (off state) reverse avalanche region anode ? forward blocking region i rrm at v rrm (off state) 180 120 120 90 figure 1. typical rms current derating figure 2. on?state power dissipation figure 3. typical on?state characteristics figure 4. typical gate trigger current versus junction temperature 8 0 i t(rms) , rms on?state current (amps) 110 i t(av) , average on?state current (amps) 38 0 3 0 3.5 0.5 v t , instantaneous on?state voltage (volts) 100 10 1 0.1 t j , junction temperature ( c) ?10 ?40 100 10 0 2.5 t c , case temperature ( c) p i gate trigger current ( a) 105 95 12 3 12 6 15 1.0 2.0 20 50 80 110 , average power dissipation (watts) (av) , instantaneous on?state current (amps) t dc 90 60 dc 30 typical @ t j = 25 c maximum @ t j = 110 c 5 1.5 45 80 4 75 85 67 9 6 7 30 12 5356595 ?25 20 30 40 50 60 70 80 90 180 60 3.0 maximum @ t j = 25 c 90 100
mcr8sd, mcr8sm, MCR8SN http://onsemi.com 4 figure 5. typical holding current versus junction temperature figure 6. typical gate trigger voltage versus junction temperature ?25 20 ?40 t j , junction temperature ( c) 10 t j , junction temperature ( c) ?25 65 ?40 0.2 20 5 , holding current ( a) i h 50 110 65 5 110 35 50 v gt , gate trigger voltage (volts) 80 1 1.0 ?10 35 95 1000 ?10 95 80 0.3 0.4 0.5 0.6 0.7 0.8 0.9 figure 7. typical latching current versus junction temperature 65 ?40 t j , junction temperature ( c) i l , latching current ( a) 10 1 ?25 5 20 50 95 1000 ?10 35 80 110 100 100
mcr8sd, mcr8sm, MCR8SN http://onsemi.com 5 package dimensions case 221a?09 issue aa to?220ab notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. style 3: pin 1. cathode 2. anode 3. gate 4. anode dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 ??? 1.15 ??? z ??? 0.080 ??? 2.04 b q h z l v g n a k f 123 4 d seating plane ?t? c s t u r j on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mcr8s/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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